1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a multipath accessible semiconductor memory device with a host interface between processors.
2. Description of the Related Art
In general a semiconductor memory device having more than one access port is called a multiport memory, and in particular a memory device having two access ports is called a dual-port memory. A typical dual-port memory is well known and used, for example, as an image processing video memory having a RAM (random access memory) port accessible in a random sequence and a SAM (serial access memory) port accessible only in a serial sequence.
Another type of multiport memory includes an array of memory cells, e.g., DRAM (dynamic random access memory) cells, that can be accessed randomly through two or more ports. This type of devices will be referred to as a multipath accessible semiconductor memory device in order to distinguish it from a multiport memory in which one of the ports only allows serial access.
In recently developed portable electronic systems, for example, handheld multimedia players or handheld phones or PDAs, etc., manufacturers have realized and produced products with multiprocessor systems that employ two or more processors as shown in FIG. 1 to achieve high speed and smooth operation.
Referring to FIG. 1, a first processor 10 and a second processor 12 are connected through a connection line L10. A NOR memory 14 and a DRAM 16 are coupled to the first processor 10 through determined buses B1-B3, and a DRAM 18 and a NAND memory 20 are coupled to the second processor 12 through determined buses B4-B6. The first processor 10 may perform a MODEM function for modulation and demodulation of a communication signal, and the second processor 12 may perform an application function such as processing communication data, games, entertainment, etc. The NOR memory 14 has a cell array configured in a NOR structure, and the NAND memory 20 has a cell array configured in a NAND structure. Both the NOR and NAND memories are nonvolatile memories having transistor memory cells with floating gates. The nonvolatile memories store data that must be retained even if power is turned off, for example, particular codes of handheld instruments and storage data. The DRAMs 16 and 18 function as main memories for the processors, but they loose their data if power is turned off.
In a multi processor system like the one shown in FIG. 1, a DRAM is allocated to every processor, and an interface such as a UART, SPI, or SRAM, all having relatively low speed, is used for communication between the processors over connection line L10. Thus, it is difficult to guarantee a satisfactory data transmission speed, and the complexity, size and expense of the memory configuration increases. Thus a scheme as shown in FIG. 2 has been developed to reduce the size, increase the data transmission speed, and reduce the number of DRAMs.
In the system of FIG. 2, as compared with the system of FIG. 1, one DRAM 17 is coupled to first and second processors 10 and 12 through buses B1 and B2. For both processors to access the one DRAM through two paths as shown in FIG. 2, the DRAM must have two ports to connect to the corresponding buses B1 and B2. However, as shown in FIG. 3, a general DRAM is a memory 1 having a single port PO.
Referring to FIG. 3 which shows the structure of a general DRAM, a memory cell array includes first to fourth banks 3, 4, 5 and 6, each corresponding to and connected to a row decoder 8 and a column decoder 7. An upper input/output sense amplifier and driver 13 is operationally coupled to the first bank 3 or third bank 5 through multiplexers 11, 12, and a lower input/output sense amplifier and driver 13 is operationally coupled to the second bank 4 or fourth bank 6 through multiplexers 14, 15. For example, in selecting a memory cell of the first bank 3 and in reading data stored in the selected memory cell, an output procedure to read the data will be described as follows. A selected word line is activated, and data in the memory cell is sensed and amplified by a bit line sense amplifier and then transferred to a local input/output line 9 according to an activation of corresponding column selection line. Data transferred to the local input/output line 9 is transferred to a global input/output line GIO by a switching operation of first multiplexer 21, and a second multiplexer 11 connected to global input/output line GIO transfers data from the global input/output line GIO to the upper input/output sense amplifier and driver 13. Data is again sensed and amplified by the upper input/output sense amplifier and driver 13 and is then output to a data output line L5 through a path unit 16. Meanwhile, in reading data stored in a memory cell of the fourth bank 6, the data is output to an output terminal DQ through a multiplexer 24, the multiplexer 14, the lower input/output sense amplifier and driver 13, the path unit 16 and the data output line L5, in that order. As described above, the DRAM 1 of FIG. 3 has a structure in which two banks share one input/output sense amplifier and driver, and is a single port memory in which data is input/output through one port PO. That is, the DRAM 1 of FIG. 3 is only applicable to the system of FIG. 1, and is inapplicable to a multiprocessor system like in FIG. 2 due to the structure of the memory bank and port.
In an effort to realize a memory adequate for a multiprocessor system like in FIG. 2, a prior art system having a configuration shown FIG. 4, in which a shared memory area can be accessed by a plurality of processors, is disclosed in US Publication No. US2003/0093628.
Referring to FIG. 4 which illustrates a multiprocessor system 50, a memory array 35 is constructed of first, second and third portions. The first portion 33 of the memory array 35 is accessed only by a first processor 70 through a port 37, the second portion 31 is accessed only by a second processor 80 through a port 38, and the third portion 32 is accessed by both of the first and second processors 70 and 80. The size of the first and second portions 33 and 31 of the memory array 35 may be flexibly changed depending upon an operating load of the first and second processors 70 and 80, and the memory array 35 may be realized by any type of memory or disk storage.
To realize the third portion 32 shared by the first and second processors 70 and 80 within the memory array 35 of a DRAM, some technical challenges must be overcome. For example, it is very important to properly layout the memory areas within the memory array 35 and input/output sense amplifiers, and to provide an adequate technique for read/write path control of each port.
Moreover, in conventional communication between processors, for example, between a MODEM and an application processor or multimedia coprocessor, a UART, SPI or SRAM interface has been used, thereby causing problems such as low operating speed, an increase in the number of pins, etc. In particular, to adequately realize a three-dimensional game or image communication, HDPDA, wibro, etc., data traffic between a MODEM and a processor must increase, so the need for a high speed-interface between processors is increasing.
Thus, better solutions are needed to the problems caused by low-speed communication interfaces and shared memory area allocated within a DRAM memory cell array.